Learn Verilog HDL and MATLAB for Signal Processing

create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports clk] Verilog code module Counter_UP_down(led, clk, sw, btn); output [3:0] led; input [1:0] sw; input [3:0] btn; input clk; reg [3:0] led; reg [26:0] count; reg clkdiv; initial begin     count = 0;     clkdiv = 0; end always @ (posedge clk) begin     if (btn[3])     begin         //count speed = high         count <= count + 1;         if(count == 12500000)         begin             count <= 0;             clkdiv <= ~clkdiv;         end     end       else         begin           //count speed = low           count <= count + 1;         ...

System tasks $time and $realtime are used to return  current simulation time. 'timescale <time unit> <time precision> Examples 'timescale   1ns/1ps 'timescale 10ns/1ns 'timescale 1ns/1ns Example-1 / Declare the timescale where time_unit is 1ns // and time_precision is 1ps `timescale 1ns / 1ps   // NOTE: Testbench is the same as in previous example module top ; // To understand the effect of timescale, let us // drive a signal with some values after some delay reg data ;   initial begin // Initialize the signal to 0 at time 0 units data <= 0 ;   // Advance by 1 time unit, display a message and toggle val # 1 $display ( "Time=%0t At time #1" , $realtime ) ; data <= 1 ;   // Advance by 0.49 time unit and toggle val # 0.49 $display ( "Time=%0t At time #0.49" , $realtime ) ; data <= 0 ;   // Advance by 0.50 time unit and toggle val # 0.50 ...