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Verilog HDL: Vectors and Arrays


Vectors:
 Nets or reg data types in verilog HDL can be declared as vectors (a word of multiple bits).

wire a;      // single bit variable.
wire [4:0]b;  //5-bit vector wire
reg clock;     // scalar register
reg [0:31] bus;  // 32-bits bus register

reg [63:0]count1;  // 64-bit register count1
reg [0:31]count2;   // 32-bit register count2

Part select of a variable vector
bus[31]=1'b0;   // set 31th bit of bus
count1[0]; // 0th bit of count1 register
count1[31-:8] ;  //// start bit=31, width=8=> data[31:24]
count1[24+:8] ;  //// start bit=24, width=8=> data[31:24]

count2[31-:8] ;  //// start bit=31, width=8=> data[24:31]
count2[24+:8] ;  //// start bit=24, width=8=> data[24:31]


//in a loop to select all bytes of the vector.
input a,b;
reg j;
reg [255:0]data1;
reg [0:255]data2;

alsways@ (a,b)
begin
for (j=0; j<=31; j=j+1)
byte = data1[(j*8)+:8]; //Sequence is [7:0], [15:8]... [255:248]

//Can initialize a part of the vector
data1[(byteNum*8)+:8] = 8'b0; //If byteNum = 1, clear 8 bits [15:8]



Arrays in Verilog HDL:

In Verilog HDL, arrays are allowed for reg, real,time, integer, realtime and vector register data types.
Multidimensional arrays can also be declared with any number of dimensions. Arrays of nets can also be used to connect ports of generated instances. Each element of the array can be used in the similar way as a scalar or vector net. Arrays are accessed <array_name>[<subscript>]. For multidimension arrays, indexes need to be provided for each dimension.

Examples of arrays:

integer mat_count[0:15];     //An array of 16 one bit integer variables

reg add[31:0];   //array of 32 one bit add register variables

time check_t[1:100]; // Array of 100 time check_t variables

reg [4:0] in_port[0:7]; // Array of 8 in_port reg type variables. each in_port is 5 bits wide.

integer mat[4:0][0:255]; // Two dimensional array of integers

reg [63:0] arr_4d [15:0][7:0][7:0][255:0]; //Four dimensional array

wire [7:0] array2 [5:0]; //  Array of 6 wires,  8 bit wide.

One should not confuse between array and vector. A vector is a single element that is n-bit wide.
However, arrays are multiple elements which is 1-bit or n-bit wide.

Examples of assignment to elements of arrays shown above are given below:

mat_count[6] = 0; // Reset 6th element of array of count variables

add[4]=1; // set 4th element of array of add variables

chk_t[100] = 0; // Reset 100th time check point value

in_port[3] = 0; // Reset 3rd element (a 5-bit value) of in_port array.

in_port = 0; // Illegal syntax - Attempt to write the entire array

mat[1][0] = 33559; // Set value of element indexed by [1][0] to 33559

arr_4d[0][0][0][0][15:0] = 0; //Clear bits 15:0 of the register
//accessed by indices [0][0][0][0]


Memories
In Verilog, memories can be modelled as an array of 1-dimensional array of registers. Each element of the array is known as an a element or word and is addressed by a single array index. Each word can be one or more bits. One should be able to differentiate one n-bit register and n 1-bit register.
A particular word in memory is obtained by using the address as a memory array subscript.

reg mem_1bit[0:1023]; // Memory mem_1bit with 1K 1-bit words. i.e. 1024 elements of 1 bit.

reg [7:0] mem_byte[0:1023]; // Memory mem_byte with 1K 8-bit. i.e. 1024 elements of 8-bits each.








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