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Verilog HDL: Structured Procedures: Initial Statement


Structured Procedures: used in behavioral modelling

There are two structured procedure statements in Verilog: always and initial. These statements are the two most basic statements in behavioral modeling. All other behavioral statements can appear only inside these structured procedure statements.

Verilog is a concurrent programming language unlike the C programming language, which is sequential in nature. Activity flows in Verilog run in parallel rather than in sequence.

Each always and initial statement represents a separate activity flow in Verilog.
Each activity flow starts at simulation time 0. The statements always and initial cannot be
nested.

1. Initial Statement

 All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes execution independently of other blocks. Multiple behavioral statements must be grouped, typically using the keywords begin and end.

Example of initial Statement

 module Testing;
reg x,y, a,b, m;
initial
m = 1'b0; //single statement; does not need to be grouped

 initial
begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;

end

 initial
begin
#10 x = 1'b0;
#25 y = 1'b1;
end

initial
#50 $finish;

endmodule

 In the above example, the three initial statements start to execute in parallel at time 0. If a
delay #<delay> is seen before a statement, the statement is executed <delay> time units
after the current simulation time.

Thus, the execution sequence of the statements inside the initial blocks will be as follows.

time statement executed
0 m = 1'b0;
5 a = 1'b1;
10 x = 1'b0;
30 b = 1'b0;
35 y = 1'b1;
50 $finish;


Data Declaration Styles in Verilog

 1.Combined Port/Data Declaration and Variable Initialization

 module adder (sum, co, a, b, ci);
output reg [7:0] sum = 0; //Initialize 8 bit output sum
output reg co = 0; //Initialize 1 bit output co
input [7:0] a, b;
input ci;
--
--

endmodule

2. Combined ANSI C Port Declaration and Variable Initialization

 module adder (output reg [7:0] sum = 0, //Initialize 8 bit output
output reg co = 0, //Initialize 1 bit output co
input [7:0] a, b,
input ci
);
--
--
endmodule

Source: S. Palnitkar

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