Getting started with MATLAB

Getting start with MATLAB

Launch MATLAB Software and type the following code on command prompt and check the output.




To initialize a scalar a:
>>a=[2]


To initialize a row vector b:

>>b=[1 2 3 4 5]

Note that spaces between numbers signify a new column.

To initialize a column vector c:

>>c=[6; 7; 8; 9]

Note that semicolons between numbers signify a new row.

To initialize a 3 by 3 matrix M:
>>M=[1 2 3; 4 5 6; 7 8 9]
Again, spaces between numbers signify a new column,
whereas semicolons signify a new row.

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Verilog HDL: Structured Procedures: Initial Statement

Structured Procedures: used in behavioral modelling There are two structured procedure statements in Verilog: always and initial. These statements are the two most basic statements in behavioral modeling. All other behavioral statements can appear only inside these structured procedure statements. Verilog is a concurrent programming language unlike the C programming language, which is sequential in nature. Activity flows in Verilog run in parallel rather than in sequence. Each always and initial statement represents a separate activity flow in Verilog. Each activity flow starts at simulation time 0. The statements always and initial cannot be nested. 1. Initial Statement All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes execution in...

Vrilog HDL: Nonblocking Procedural Assignments

Nonblocking Procedural Assignment Nonblocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block. A <= operator is used to specify nonblocking assignments. Note that this operator has the same symbol as a relational operator, less_than_equal_to. The operator <= is interpreted as a relational operator in an expression and as an assignment operator in the context of a nonblocking assignment. To illustrate the behavior of nonblocking statements and its difference from blockinglets take an example. Example: reg x, y, z; reg [15:0] reg_a, reg_b; integer count; //All behavioral statements must be inside an initial or always block initial begin x = 0; y = 1; z = 1; //Scalar assignments count = 0; //Assignment to integer variables reg_a = 16'b0; reg_b = reg_a; //Initialize vectors reg_a[2] <= #15 1'b1; //Bit select assignment with delay reg_b[15:13] <= #10 {x, y, z}; //Assign result ...

Part-3 Example of Sequential Circuits

Example-1 A 4-Bit Shift register with asynchronous load. module bit4_SHreg(R,L,w,clk,Q); input [3:0]R; input L,w,clk; output reg [3:0]Q; always@(posedge L,posedge clk) //begin if (L) Q<=R; else begin Q[0]<=Q[1]; Q[1]<=Q[2]; Q[2]<=Q[3]; Q[3]<=w; /// w is data input /// w-> Q3 -> Q2-> Q1->Q0 end endmodule Test Bench module test_bit4SHreg; reg [3:0]R; reg L,w,clk; wire [3:0]Q; bit4_SHreg r0(R,L,w,clk,Q); initial begin clk=0; L=0;w=0;R=0; $monitor("R=%d,w=%b,Q=%b",R,w,Q); end always #5 clk=~clk; initial begin #1 L=1; R=6; #7 L=0; w=1; #8 w=0; #9 w=1; #9 w=0; #9 w=1; #9 L=1; R=5; #3 R=4; #5 R=7; end endmodule Simulation Results ...

Learn Verilog HDL and MATLAB for Signal Processing

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