Skip to main content

Verilog HDL: Blocking and nonblocking Assignments



There are two types of procedural assignment statements: blocking and non-blocking


   1. Blocking Assignments:

    Blocking assignment statements are executed in the order they are specified in a sequential block.      A blocking assignment will not block execution of statements that follow in a parallel block. The =    operator is used to specify blocking assignments.

 Example:

reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;

//All behavioral statements must be inside an initial or always block
initial
begin
x = 0;
y = 1;
z = 1;                                //Scalar assignments
count = 0;                         //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //initialize vectors
#10 reg_a[2] = 1'b1; //Bit select assignment with delay
#15 reg_b[15:13] = {x, y, z} //Assign result of concatenation to
                                              // part select of a vector
count = count + 1;                 //Assignment to an integer (increment)
end


In the given example, the statement y = 1 is executed only after x = 0 is executed. The
behavior in a particular block is sequential in a begin-end block if blocking statements are
used, because the statements can execute only in sequence.
The statement count = count + 1 is executed last.

The simulation times at which the statements are executed are as follows:
• All statements x = 0 through reg_b = reg_a are executed at time 0
• Statement reg_a[2] = 0 at time = 10
• Statement reg_b[15:13] = {x, y, z} at time = 25
• Statement count = count + 1 at time = 25
• Since there is a delay of 10 and 15 in the preceding statements, count = count + 1
will be executed at time = 25 units

Note that for procedural assignments to registers, if the right-hand side has more bits than
the register variable, the right-hand side is truncated to match the width of the register
variable. The least significant bits are selected and the most significant bits are discarded.
If the right-hand side has fewer bits, zeros are filled in the most significant bits of the
register variable.

Ref: S. Palnitkar


Comments

Post a Comment

Popular posts from this blog

Verilog HDL: Structured Procedures: Initial Statement

Structured Procedures: used in behavioral modelling There are two structured procedure statements in Verilog: always and initial. These statements are the two most basic statements in behavioral modeling. All other behavioral statements can appear only inside these structured procedure statements. Verilog is a concurrent programming language unlike the C programming language, which is sequential in nature. Activity flows in Verilog run in parallel rather than in sequence. Each always and initial statement represents a separate activity flow in Verilog. Each activity flow starts at simulation time 0. The statements always and initial cannot be nested. 1. Initial Statement All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes execution in
Post a Comment
Read more

VERILOG HDL: Vectors and arrays

Vectors:  Nets or reg data types in verilog HDL can be declared as vectors (a word of multiple bits). wire a;      // single bit variable. wire [4:0]b;  //5-bit vector wire reg clock;     // scalar register reg [0:31] bus;  // 32-bits bus register reg [63:0]count1;  // 64-bit register count1 reg [0:31]count2;   // 32-bit register count2 Part select of a variable vector bus[31]=1'b0;   // set 31th bit of bus count1[0]; // 0th bit of count1 register count1[31-:8] ;  //// start bit=31, width=8=> data[31:24] count1[24+:8] ;  //// start bit=24, width=8=> data[31:24] count2[31-:8] ;  //// start bit=31, width=8=> data[24:31] count2[24+:8] ;  //// start bit=24, width=8=> data[24:31] //in a loop to select all bytes of the vector. input a,b; reg j; reg [255:0]data1; reg [0:255]data2; alsways@ (a,b) begin for (j=0; j<=31; j=j+1) byte = data1[(j*8)+:8]; //Sequence is [7:0], [15:8]... [255:248] //Can initialize a part of the vector data1[(byteN
Post a Comment
Read more

Vrilog HDL: Nonblocking Procedural Assignments

Nonblocking Procedural Assignment Nonblocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block. A <= operator is used to specify nonblocking assignments. Note that this operator has the same symbol as a relational operator, less_than_equal_to. The operator <= is interpreted as a relational operator in an expression and as an assignment operator in the context of a nonblocking assignment. To illustrate the behavior of nonblocking statements and its difference from blockinglets take an example. Example: reg x, y, z; reg [15:0] reg_a, reg_b; integer count; //All behavioral statements must be inside an initial or always block initial begin x = 0; y = 1; z = 1; //Scalar assignments count = 0; //Assignment to integer variables reg_a = 16'b0; reg_b = reg_a; //Initialize vectors reg_a[2] <= #15 1'b1; //Bit select assignment with delay reg_b[15:13] <= #10 {x, y, z}; //Assign result
Post a Comment
Read more