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Verilog HDL: Examples of always blocks


always @ Block Examples:

 1. Register is triggered by positive edged clock

module register(Q, D, clock);
input  D, clock;
output Q;
reg Q;                                                //A real register. Holds Q between clock edges.
always @(posedge clock) begin
Q <= D;
end
endmodule

2. AND gate
module and_gate(out, in1, in2);
input in1, in2;
output out;
reg out;                                          // Not a real register, holds assignments in always block
always @(in1 or in2) begin
out = in1 & in2;                            // The compiler will not synthesize this code to a register, because
                                                       //out changes whenever in1 or in2 change.
end
endmodule

3. Incomplete sensitivity list or incomplete assignment

 (i) What if you omit an input trigger (e.g. in2)
(ii) Compiler will insert a latch to hold the state
(iii) Becomes a sequential circuit — NOT what you want

module and_gate (out, in1, in2);
input in1, in2;
output out;
reg out;                                      // Real register!! Holds out because in2 isn’t specified in always                                                            // sensitivity list
always @(in1) begin
out = in1 & in2;
end
endmodule

 Rules:
1) Include all inputs in the trigger list for a combinational circuit.
2) Use complete assignments
⇒ Every path must lead to an assignment for out
⇒ Otherwise out needs a state element


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