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Verilog HDL: Delays


Delays in Verilog HDL


1. Inter Assignment or regular delay control:

Regular delay is used to assign a specified nonzero delay to the left of a procedural assignment.  the delay value is assigned using parameters. It is suggested to use parameters to define constant variable so that it can be change the programming easy. The example is as follows.

Example:

//use parameters
parameter latency = 25;
parameter delta = 5;
//declare register variables
reg a, b, c, x, y;
initial
begin

a = 0; // no delay control
#15 b = 1; // delay control with a number. Delay execution of
// b = 1 by 10 units
#latency c = 0; // Delay control with identifier. Delay of 25 units
#(latency + delta) x = 1; // Delay control with expression
#b a = a + 1; // Delay control with identifier. Take value of b

#(4:5:6) q = 0; // Minimum, typical and maximum delay values.
end

In the above example, the execution of a procedural assignment is delayed by the number
specified by the delay control. For begin-end groups, delay is always relative to time
when the statement is encountered. Thus, b =1 is executed 15 units after it is encountered
in the activity flow.

2. Intra delay:
To introduce this delay in a verilog statement, delay is introduced at the right hand side of the assignment operator instead of left hand side. Such delay changes the flow of activity compared to regular manner.

Example: Intra assignment delays:

module mod(input x, input y, output reg z);

reg a,b,c;

//initial assignment delays

initial
begin
                        a=1'b0;                         //execute at 0 time unit
                        b=#10 1'b1;                  //execute at 10 time unit
                       z=#5 (x+y);                   // //execute at 15 time unit
                      c=#6 (z+3);                   ///execute at 21 time unit

end

endmodule

                   






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