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Verilog HDL: Structured Procedure: Always statement


Always statement:

All behavioral statements inside an always statement constitute an always block. The always statement starts at time 0 and executes the statements in the always block continuously in a looping fashion.  This statement is used to model a block of activity that is repeated continuously in a digital circuit. An example is a clock generator module that toggles the clock signal every half cycle. In real circuits, the clock generator is active from time 0 to as long as the circuit is powered on.

Example:

module clock_gen (output reg clock);
//Initialize clock at time zero
initial
clock = 1'b0;
//Toggle clock every half-cycle (time period = 20)
always
#10 clock = ~clock;

initial
#1000 $finish;
endmodule


In the given example, the always statement starts at time 0 and executes the statement clock =
~clock every 10 time units. Notice that the initialization of clock has to be done inside a
separate initial statement. If we put the initialization of clock inside the always block,
clock will be initialized every time the always is entered.

Also, the simulation must be halted inside an initial statement. If there is no $stop or $finish statement to halt the simulation, the clock generator will run forever.

C programmers might draw an analogy between the always block and an infinite loop.
But hardware designers tend to view it as a continuously repeated activity in a digital
circuit starting from power on. The activity is stopped only by power off ($finish) or by
an interrupt ($stop).

Source: S. Palnitkar

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