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Part-1 Verilog Examples for Sequential circuits


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Counters with synchronous and asynchronous reset

 Example-1 Verilog code for an n-bit Up-counter with enable (en), load (l) and asynchronous reset with test bench.

module upcount(r,rst,clk,en,l,Q);
parameter n=16;
input [n-1:0]r;
input rst,clk,en,l;
output reg [n-1:0]Q;
always@(negedge rst, posedge clk)  // asynchronous clear, posedge triggered clock a
begin
if(!rst)
Q<=0;
else if (l)  // synchronous load from R
Q<=r;
else if(en)      //counts up if en=1
Q<=Q+1;
end
endmodule

Test Bench with a clock of time period 10 time units

 module test_upcount;
parameter n=16;
reg [n-1:0]r;
reg rst,clk,en,l;
wire [n-1:0]Q;

upcount t0(r,rst,clk,en,l,Q);

initial
begin
clk=0; l=0;en=0;rst=0;r=0;
$monitor("r=%b,en=%b,l=%b,Q=%d \n",r,en,l,Q);
end

always
#5 clk=~clk;

initial
begin
#1 rst=1;
#7 l=1;en=0;r=1;
#5en=1;l=0;
#6 r=0; l=1;en=0;
#5en=1;l=0;
#5en=0;l=0;
#5en=1;l=0;
end
endmodule


Simulation Results


Synthesis Schematic








































Example-2 Verilog code for an n-bit Up-counter with enable (en), load (l) and synchronous reset with test bench.
module upcount(r,rst,clk,en,l,Q);
parameter n=16;
input [n-1:0]r;
input rst,clk,en,l;
output reg [n-1:0]Q;
always@(posedge clk)  // synchronous reset, posedge triggered clock a
begin
if(!rst)
Q<=0;
else if (l)  // synchronous load from R
Q<=r;
else if(en)      //counts up if en=1
Q<=Q+1;
end
endmodule

Test Bench with a clock of time period 10 time units

module test_syn_rstUPcount;

parameter n=16;

reg [n-1:0]r;

reg rst,clk,en,l;

wire [n-1:0]Q;


upcount_syn_reset r1(r,rst,clk,en,l,Q);


initial

begin

clk=0; l=0;en=0;rst=0;r=0;

$monitor("r=%b,en=%b,l=%b,Q=%d \n",r,en,l,Q);

end


always

#5 clk=~clk;

initial

begin

#1 rst=1;

#3 l=1;en=0;r=16;

#9 en=1;l=0;
#10 en=1;
#30 rst=0;
#10 rst=1; r=18; l=1;en=0;
#10 r=20;
#10 r=25;
#10 en=1;
#40 en=0;l=0; rst=0;

end

endmodule



Simulation Results










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