Skip to main content

Part-2 Verilog Examples for Sequential circuits



Find MATlAB Programs for signals and systems with output here↓ 
https://meenakshiagarwalvlsi.blogspot.com/p/graphical-representation-of-time.html


Example-1 Verilog code for an arbitrary size register

// N-bit register with Asynchronous reset

module n_bitreg(D,clk,clr,Q);
    parameter n=16;
    input [n-1:0]D;
    input clk,clr;
    output reg[n-1:0] Q;
 
    always@(negedge clr, posedge clk)
    begin
    if(!clr)     ///asynchronous clear active low
    Q<=0;
    else
    Q<=D;
    end
endmodule


//Test Bench


module test_regNbit;
parameter n=16; 
reg [n-1:0]D;
reg clk,clr;
wire [n-1:0]Q;

n_bitreg r1(D,clk,clr,Q);

initial
begin
clk=0; clr=0;D=0;
$monitor("D=%d,Q=%d",D,Q);
end

always
#5 clk=~clk;

initial
begin
#1 clr=1;
D=8;
#5 clr=0; D=7;
#8 clr=1; D=12;
#5 D=11;
#9 D=13;
#9 D=64;
end

endmodule

//Simulation Waveform


//Sythesized Schematic



Example-2    Verilog code for a D-Flip flop where input D is applied using a Mutiplexer. 
Note: Example -1 and Example -2 are entirely different.

module dff_mux(
Fig. - D-Flip flip with input from 2:1 Mux
    input d0,
    input d1,
    input sel,
    input clk,
    output reg q                       
    );
    always @(posedge clk)
    begin
    if(sel==1)                                                                
    q<=d1;
    else
    q<=d0;
    end
       
endmodule   //mux_D Flip flop

Test Bench


module test_Dff_mux;
reg d0,d1,sel,clk;
    wire q;
dff_mux m1(d0,d1,sel,clk,q);                       // 2 data input d0 and d1 controlled by sel
    
    initial
begin
clk=0; sel=0;d0=0;d1=1;
$monitor("d0=%d,d1=%b,q=%b",d0,d1,q);
end

always
#5 clk=~clk;

initial
begin
#1 sel=1;
d0=0;d1=1;
#7 sel=0; d0=0;
#8 sel=1; d1=1;
#9 sel=0; d0=1; d1=0;
#9 sel=1; d0=0; d1=0;
#9 sel=0; d0=1; d1=0;
#9 sel=1; d0=0; d1=0;
#9 sel=0; d0=1; d1=0;
#9 sel=1; d0=0; d1=0;
#9 sel=0; d0=1; d1=0;
#9 sel=1; d0=0; d1=0;

end
endmodule

Simulation Results

Synthesized Schematic


Comments

Post a Comment

Popular posts from this blog

Verilog HDL: Structured Procedures: Initial Statement

Structured Procedures: used in behavioral modelling There are two structured procedure statements in Verilog: always and initial. These statements are the two most basic statements in behavioral modeling. All other behavioral statements can appear only inside these structured procedure statements. Verilog is a concurrent programming language unlike the C programming language, which is sequential in nature. Activity flows in Verilog run in parallel rather than in sequence. Each always and initial statement represents a separate activity flow in Verilog. Each activity flow starts at simulation time 0. The statements always and initial cannot be nested. 1. Initial Statement All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes execution in...
Post a Comment
Read more

Vrilog HDL: Nonblocking Procedural Assignments

Nonblocking Procedural Assignment Nonblocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block. A <= operator is used to specify nonblocking assignments. Note that this operator has the same symbol as a relational operator, less_than_equal_to. The operator <= is interpreted as a relational operator in an expression and as an assignment operator in the context of a nonblocking assignment. To illustrate the behavior of nonblocking statements and its difference from blockinglets take an example. Example: reg x, y, z; reg [15:0] reg_a, reg_b; integer count; //All behavioral statements must be inside an initial or always block initial begin x = 0; y = 1; z = 1; //Scalar assignments count = 0; //Assignment to integer variables reg_a = 16'b0; reg_b = reg_a; //Initialize vectors reg_a[2] <= #15 1'b1; //Bit select assignment with delay reg_b[15:13] <= #10 {x, y, z}; //Assign result ...
Post a Comment
Read more

Part-3 Example of Sequential Circuits

Example-1 A 4-Bit Shift register with asynchronous load. module bit4_SHreg(R,L,w,clk,Q);     input [3:0]R;     input L,w,clk;     output reg [3:0]Q; always@(posedge L,posedge clk) //begin if (L) Q<=R; else begin Q[0]<=Q[1]; Q[1]<=Q[2]; Q[2]<=Q[3]; Q[3]<=w;            /// w is data input                            /// w-> Q3 -> Q2-> Q1->Q0 end endmodule Test Bench module test_bit4SHreg; reg [3:0]R;    reg L,w,clk;   wire [3:0]Q;       bit4_SHreg r0(R,L,w,clk,Q);         initial begin clk=0; L=0;w=0;R=0; $monitor("R=%d,w=%b,Q=%b",R,w,Q); end always #5 clk=~clk; initial begin #1 L=1; R=6; #7 L=0; w=1; #8 w=0;  #9 w=1; #9 w=0; #9 w=1; #9 L=1; R=5; #3 R=4; #5 R=7; end    endmodule Simulation Results ...
1 comment
Read more