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Part-2 Verilog Examples for Sequential circuits



Find MATlAB Programs for signals and systems with output here↓ 
https://meenakshiagarwalvlsi.blogspot.com/p/graphical-representation-of-time.html


Example-1 Verilog code for an arbitrary size register

// N-bit register with Asynchronous reset

module n_bitreg(D,clk,clr,Q);
    parameter n=16;
    input [n-1:0]D;
    input clk,clr;
    output reg[n-1:0] Q;
 
    always@(negedge clr, posedge clk)
    begin
    if(!clr)     ///asynchronous clear active low
    Q<=0;
    else
    Q<=D;
    end
endmodule


//Test Bench


module test_regNbit;
parameter n=16; 
reg [n-1:0]D;
reg clk,clr;
wire [n-1:0]Q;

n_bitreg r1(D,clk,clr,Q);

initial
begin
clk=0; clr=0;D=0;
$monitor("D=%d,Q=%d",D,Q);
end

always
#5 clk=~clk;

initial
begin
#1 clr=1;
D=8;
#5 clr=0; D=7;
#8 clr=1; D=12;
#5 D=11;
#9 D=13;
#9 D=64;
end

endmodule

//Simulation Waveform


//Sythesized Schematic



Example-2    Verilog code for a D-Flip flop where input D is applied using a Mutiplexer. 
Note: Example -1 and Example -2 are entirely different.

module dff_mux(
Fig. - D-Flip flip with input from 2:1 Mux
    input d0,
    input d1,
    input sel,
    input clk,
    output reg q                       
    );
    always @(posedge clk)
    begin
    if(sel==1)                                                                
    q<=d1;
    else
    q<=d0;
    end
       
endmodule   //mux_D Flip flop

Test Bench


module test_Dff_mux;
reg d0,d1,sel,clk;
    wire q;
dff_mux m1(d0,d1,sel,clk,q);                       // 2 data input d0 and d1 controlled by sel
    
    initial
begin
clk=0; sel=0;d0=0;d1=1;
$monitor("d0=%d,d1=%b,q=%b",d0,d1,q);
end

always
#5 clk=~clk;

initial
begin
#1 sel=1;
d0=0;d1=1;
#7 sel=0; d0=0;
#8 sel=1; d1=1;
#9 sel=0; d0=1; d1=0;
#9 sel=1; d0=0; d1=0;
#9 sel=0; d0=1; d1=0;
#9 sel=1; d0=0; d1=0;
#9 sel=0; d0=1; d1=0;
#9 sel=1; d0=0; d1=0;
#9 sel=0; d0=1; d1=0;
#9 sel=1; d0=0; d1=0;

end
endmodule

Simulation Results

Synthesized Schematic


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