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Part-3 Example of Sequential Circuits

Example-1 A 4-Bit Shift register with asynchronous load.

module bit4_SHreg(R,L,w,clk,Q);
    input [3:0]R;
    input L,w,clk;
    output reg [3:0]Q;

always@(posedge L,posedge clk)
//begin
if (L)
Q<=R;
else
begin
Q[0]<=Q[1];
Q[1]<=Q[2];
Q[2]<=Q[3];
Q[3]<=w;            /// w is data input
                           /// w-> Q3 -> Q2-> Q1->Q0
end

endmodule

Test Bench
module test_bit4SHreg;
reg [3:0]R;
   reg L,w,clk;
  wire [3:0]Q;
  
   bit4_SHreg r0(R,L,w,clk,Q);
   
   
initial
begin
clk=0; L=0;w=0;R=0;
$monitor("R=%d,w=%b,Q=%b",R,w,Q);
end

 always
#5 clk=~clk;

 initial
begin
#1 L=1; R=6;
#7 L=0; w=1;
#8 w=0; 
#9 w=1;
#9 w=0;
#9 w=1;
#9 L=1; R=5;
#3 R=4;
#5 R=7;
end
  

endmodule

Simulation Results



Example-2 A 4-Bit Shift register with Synchronous load.

module bit4_SHregSyncL(R,L,w,clk,Q);
    input [3:0]R;
    input L,w,clk;
    output reg [3:0]Q;

always@(posedge clk)
//begin
if (L)
Q<=R;
else
begin
Q[0]<=Q[1];
Q[1]<=Q[2];
Q[2]<=Q[3];
Q[3]<=w;            /// w is data input
                           /// w-> Q3 -> Q2-> Q1->Q0
end

endmodule

Test Bench


module test_bit4SHreg;
reg [3:0]R;
   reg L,w,clk;
  wire [3:0]Q;
  
   bit4_SHregSyncL r1(R,L,w,clk,Q);
   
   
initial
begin
clk=0; L=0;w=0;R=0;
$monitor("R=%d,w=%b,Q=%b",R,w,Q);
end

always
#5 clk=~clk;

initial
begin
#1 L=1; R=6;
#7 L=0; w=1;
#8 w=0; 
#9 w=1;
#9 w=0;
#9 w=1;
#9 L=1; R=5;
#3 R=4;
#5 R=7;
end
  
endmodule


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