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Various examples of RTL design have been given as follows:

 Example 1 : Verilog code for a 4-bit gray to binary converter using structure modelling.
module gray2bin( input [3:0] G, output [3:0] B ); assign B[3]=G[3]; xor x1(B[2],B[3],G[2]); xor x2(B[1],B[2],G[1]); xor x3(B[0],B[1],G[0]); endmodule

Test bench



`timescale 1ns / 1ps
module gray_binT;
reg [3:0] G1;
   wire [3:0] B1;
   gray2bin g1(G1,B1);
   initial 
   begin
   $monitor("Gray code values=%b, Binary Values=%b",G1,B1);
   //$monitor("Binary values of grey codes=%b",B1);
   end
   initial
   begin
   G1=4'd0;
   #6 G1=4'b0001;
   #4G1=4'd2;
   #6 G1=4'd3;
   #6 G1=4'd4;
      #4G1=4'd5;
      #6 G1=4'd6;
      #6 G1=4'd7;
         #4G1=4'd8;
         #6 G1=4'd9;
         #6 G1=4'd10;
            #4G1=4'd11;
            #6 G1=4'd12;
             #6 G1=4'd13;
                    #6 G1=4'd14;
                       #4G1=4'd15;
                       #6 G1=4'd0;
                  
   end
   
   endmodule

Example 2 : Verilog code for a 2_2 Binary Multiplier.
module multi_2_2(
    input [1:0] a,
    input [1:0] b,
    output [3:0] y
    );
 
    wire w1,w2,w3,w4;
    assign y[0]=a[0]& b[0];
    assign w1=a[0]& b[1];
    assign w2=a[1]& b[0];
    assign w3=a[1]& b[1];
 
    full_add f0(w1,w2,1'b0,y[1],w4),
             f1(w3,1'b0,w4,y[2],y[3]);
             

endmodule

module full_add(
    input A,
    input B,
    input C,
    input S,
    input Cr
    );
 
    assign {Cr,S}=A+B+C;
 
endmodule

Test Bench for Multiplier
module multi_test;

  reg [1:0] x1,y1;
 wire [3:0]z ;

 initial 
    begin
    $monitor("value of input number x1=%b, value of input number y1=%b, Multiplication output=%b",x1,y1,z);
        end

 multi_2_2 m0(x1,y1,z);
 initial 
 begin
 x1=0;y1=0;
 #1 x1=2'd0; y1=2'd0;
 #5 x1=2'd0 ;y1=2'd1;
 #1 x1=2'd0; y1=2'd2;
 #5 x1=2'd0 ;y1=2'd3;
 #1 x1=2'd1; y1=2'd1;
 #5 x1=2'd1 ;y1=2'd2;
 #1 x1=2'd1; y1=2'd3;
 #5 x1=2'd1 ;y1=2'd4;
  #1 x1=2'd2; y1=2'd1;
  #5 x1=2'd2 ;y1=2'd2;
  #1 x1=2'd2; y1=2'd3;
  #5 x1=2'd2 ;y1=2'd4;
  #1 x1=2'd3; y1=2'd1;
   #5 x1=2'd3 ;y1=2'd2;
   #1 x1=2'd3; y1=2'd3;
   #5 x1=2'd3 ;y1=2'd2;
     
 end
 endmodule

Simulation Output


Synthesized Schematic






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