Learn Verilog HDL and MATLAB for Signal Processing

Example-1 A 4-Bit Shift register with asynchronous load. module bit4_SHreg(R,L,w,clk,Q);     input [3:0]R;     input L,w,clk;     output reg [3:0]Q; always@(posedge L,posedge clk) //begin if (L) Q<=R; else begin Q[0]<=Q[1]; Q[1]<=Q[2]; Q[2]<=Q[3]; Q[3]<=w;            /// w is data input                            /// w-> Q3 -> Q2-> Q1->Q0 end endmodule Test Bench module test_bit4SHreg; reg [3:0]R;    reg L,w,clk;   wire [3:0]Q;       bit4_SHreg r0(R,L,w,clk,Q);         initial begin clk=0; L=0;w=0;R=0; $monitor("R=%d,w=%b,Q=%b",R,w,Q); end always #5 clk=~clk; initial begin #1 L=1; R=6; #7 L=0; w=1; #8 w=0;  #9 w=1; #9 w=0; #9 w=1; #9 L=1; R=5; #3 R=4; #5 R=7; end    endmodule Simulation Results ...

Find MATlAB Programs for signals and systems with output here↓  https://meenakshiagarwalvlsi.blogspot.com/p/graphical-representation-of-time.html Example-1 Verilog code for an arbitrary size register // N-bit register with Asynchronous reset module n_bitreg(D,clk,clr,Q);     parameter n=16;     input [n-1:0]D;     input clk,clr;     output reg[n-1:0] Q;       always@(negedge clr, posedge clk)     begin     if(!clr)     ///asynchronous clear active low     Q<=0;     else     Q<=D;     end endmodule //Test Bench module test_regNbit; parameter n=16;  reg [n-1:0]D; reg clk,clr; wire [n-1:0]Q; n_bitreg r1(D,clk,clr,Q); initial begin clk=0; clr=0;D=0; $monitor("D=%d,Q=%d",D,Q); end always #5 clk=~clk; initial begin #1 clr=1; D=8; #5 clr=0; D=7; #8 clr=1; D=12; #5 D=1...

Find MATlAB Programs for signals and systems with output here↓  https://meenakshiagarwalvlsi.blogspot.com/p/graphical-representation-of-time.html Counters with synchronous and asynchronous reset Example-1 Verilog code for an n-bit Up-counter with enable (en), load (l) and asynchronous reset with test bench. module upcount(r,rst,clk,en,l,Q); parameter n=16; input [n-1:0]r; input rst,clk,en,l; output reg [n-1:0]Q; always@(negedge rst, posedge clk)  // asynchronous clear, posedge triggered clock a begin if(!rst) Q<=0; else if (l)  // synchronous load from R Q<=r; else if(en)      //counts up if en=1 Q<=Q+1; end endmodule Test Bench with a clock of time period 10 time units module test_upcount; parameter n=16; reg [n-1:0]r; reg rst,clk,en,l; wire [n-1:0]Q; upcount t0(r,rst,clk,en,l,Q); initial begin clk=0; l=0;en=0;rst=0;r=0; $monitor("r=%b,en=%b,l=%b,Q=%d \n",r,en,l,Q); end always #5 clk=~clk; initial begi...

Various examples of RTL design have been given as follows: Example 1  : Verilog code for a 4-bit gray to binary converter using structure modelling. module gray2bin( input [3:0] G, output [3:0] B ); assign B[3]=G[3]; xor x1(B[2],B[3],G[2]); xor x2(B[1],B[2],G[1]); xor x3(B[0],B[1],G[0]); endmodule Test bench `timescale 1ns / 1ps module gray_binT; reg [3:0] G1;    wire [3:0] B1;    gray2bin g1(G1,B1);    initial     begin    $monitor("Gray code values=%b, Binary Values=%b",G1,B1);    //$monitor("Binary values of grey codes=%b",B1);    end    initial    begin    G1=4'd0;    #6 G1=4'b0001;    #4G1=4'd2;    #6 G1=4'd3;    #6 G1=4'd4;       #4G1=4'd5;       #6 G1=4'd6;       #6 G1=4'd7;    ...

Vectors:  Nets or reg data types in verilog HDL can be declared as vectors (a word of multiple bits). wire a;      // single bit variable. wire [4:0]b;  //5-bit vector wire reg clock;     // scalar register reg [0:31] bus;  // 32-bits bus register reg [63:0]count1;  // 64-bit register count1 reg [0:31]count2;   // 32-bit register count2 Part select of a variable vector bus[31]=1'b0;   // set 31th bit of bus count1[0]; // 0th bit of count1 register count1[31-:8] ;  //// start bit=31, width=8=> data[31:24] count1[24+:8] ;  //// start bit=24, width=8=> data[31:24] count2[31-:8] ;  //// start bit=31, width=8=> data[24:31] count2[24+:8] ;  //// start bit=24, width=8=> data[24:31] //in a loop to select all bytes of the vector. input a,b; reg j; reg [255:0]data1; reg [0:255]data2; alsways@ (a,b) begin for (j=0; j<=31; j=j+1) byte = data1[(j*8)+:8]; //Sequenc...

Delays in Verilog HDL 1. Inter Assignment or regular delay control: Regular delay is used to assign a specified nonzero delay to the left of a procedural assignment.  the delay value is assigned using parameters. It is suggested to use parameters to define constant variable so that it can be change the programming easy. The example is as follows. Example: //use parameters parameter latency = 25; parameter delta = 5; //declare register variables reg a, b, c, x, y; initial begin a = 0; // no delay control #15 b = 1; // delay control with a number. Delay execution of // b = 1 by 10 units #latency c = 0; // Delay control with identifier. Delay of 25 units #(latency + delta) x = 1; // Delay control with expression #b a = a + 1; // Delay control with identifier. Take value of b #(4:5:6) q = 0; // Minimum, typical and maximum delay values. end In the above example, the execution of a procedural assignment is delayed by the number specified by the delay control...

    MATLAB programs to generate and plot the following discrete time sequences: (a)     unit sample sequence del(n), (b) unit step sequence u(n), (c) ramp sequence r(n), (d) real-valued     exponential sequence x(n) = (0.8)^n u(n) for 0 < n < 50.     n=-10:10; deltan=1.*(n==0); subplot(411); stem(n,deltan,"."); xlabel("n"); ylabel("delta"); title("delta func"); %unit stepfunction step=1.*(n>=0); subplot(412); stem(n,step,"."); xlabel("n"); ylabel("u(n)"); title("unit step func"); %unit ramp ramp=n.*(n>=0); subplot(413); stem(n,ramp,"."); xlabel("n"); ylabel("r(n)"); title("unit ramp func"); %exponential signal n=0:50; xn=0.8.^n; subplot(414); stem(n,xn,"."); xlabel("n"); ylabel("x(n)"); title("unit exp func");