Learn Verilog HDL and MATLAB for Signal Processing

Delays in Verilog HDL 1. Inter Assignment or regular delay control: Regular delay is used to assign a specified nonzero delay to the left of a procedural assignment.  the delay value is assigned using parameters. It is suggested to use parameters to define constant variable so that it can be change the programming easy. The example is as follows. Example: //use parameters parameter latency = 25; parameter delta = 5; //declare register variables reg a, b, c, x, y; initial begin a = 0; // no delay control #15 b = 1; // delay control with a number. Delay execution of // b = 1 by 10 units #latency c = 0; // Delay control with identifier. Delay of 25 units #(latency + delta) x = 1; // Delay control with expression #b a = a + 1; // Delay control with identifier. Take value of b #(4:5:6) q = 0; // Minimum, typical and maximum delay values. end In the above example, the execution of a procedural assignment is delayed by the number specified by the delay control...

    MATLAB programs to generate and plot the following discrete time sequences: (a)     unit sample sequence del(n), (b) unit step sequence u(n), (c) ramp sequence r(n), (d) real-valued     exponential sequence x(n) = (0.8)^n u(n) for 0 < n < 50.     n=-10:10; deltan=1.*(n==0); subplot(411); stem(n,deltan,"."); xlabel("n"); ylabel("delta"); title("delta func"); %unit stepfunction step=1.*(n>=0); subplot(412); stem(n,step,"."); xlabel("n"); ylabel("u(n)"); title("unit step func"); %unit ramp ramp=n.*(n>=0); subplot(413); stem(n,ramp,"."); xlabel("n"); ylabel("r(n)"); title("unit ramp func"); %exponential signal n=0:50; xn=0.8.^n; subplot(414); stem(n,xn,"."); xlabel("n"); ylabel("x(n)"); title("unit exp func");

MATLAB program to generate and plot the following continuous-time signals: (a) unit impulse, δ(t), (b) unit step, u(t), (c) unit ramp, r(t), (d) parabolic signal, (e) signum function, (f) sinc function. MATLAB program: clc; clear all; close all; tmin=-10; tmax=10; dt=0.1; t=tmin:dt:tmax; %*** Impulse function δ(t) ******* delta=1.*(t==0); subplot(231);plot(t,delta); xlabel(’t’);ylabel(’delta(t)’); title(’Unit Impulse function’); %****Unit step function *** step=1.*(t>=0); subplot(232);plot(t,step); xlabel("t");ylabel("u(t)"); title("Unit Step function"); %*** Unit Ramp function *** ramp=t.*(t>=0); subplot(233);plot(t,ramp); xlabel("t");ylabel("r(t)"); title("Unit Ramp function"); %** Unit parabolic function ** parabolic=(t.^2)/2.*(t>=0); subplot(234);plot(t,parabolic); xlabel("t");ylabel("p(t)"); title("Unit Parabolic function"); %** Signum function **...

Nonblocking Procedural Assignment Nonblocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block. A <= operator is used to specify nonblocking assignments. Note that this operator has the same symbol as a relational operator, less_than_equal_to. The operator <= is interpreted as a relational operator in an expression and as an assignment operator in the context of a nonblocking assignment. To illustrate the behavior of nonblocking statements and its difference from blockinglets take an example. Example: reg x, y, z; reg [15:0] reg_a, reg_b; integer count; //All behavioral statements must be inside an initial or always block initial begin x = 0; y = 1; z = 1; //Scalar assignments count = 0; //Assignment to integer variables reg_a = 16'b0; reg_b = reg_a; //Initialize vectors reg_a[2] <= #15 1'b1; //Bit select assignment with delay reg_b[15:13] <= #10 {x, y, z}; //Assign result ...

There are two types of procedural assignment statements: blocking and non-blocking   1. Blocking Assignments:    Blocking assignment statements are executed in the order they are specified in a sequential block.      A blocking assignment will not block execution of statements that follow in a parallel block. The =    operator is used to specify blocking assignments.  Example: reg x, y, z; reg [15:0] reg_a, reg_b; integer count; //All behavioral statements must be inside an initial or always block initial begin x = 0; y = 1; z = 1;                                //Scalar assignments count = 0;                         //Assignment to integer variables reg_a = 16'b0; reg_b = reg_a; //initialize vectors #10 reg_a[2] = 1'b1; //Bit select assignment with delay #15 reg_b[15:13] = {...

always @ Block Examples: 1. Register is triggered by positive edged clock module register(Q, D, clock); input  D, clock; output Q; reg Q;                                                //A real register. Holds Q between clock edges. always @(posedge clock) begin Q <= D; end endmodule 2. AND gate module and_gate(out, in1, in2); input in1, in2; output out; reg out;                                          // Not a real register, holds assignments in always block always @(in1 or in2) begin out = in1 & in2;                            // The compiler will not synthesize this code to a register, because                   ...

Always statement: All behavioral statements inside an always statement constitute an always block. The always statement starts at time 0 and executes the statements in the always block continuously in a looping fashion.  This statement is used to model a block of activity that is repeated continuously in a digital circuit. An example is a clock generator module that toggles the clock signal every half cycle. In real circuits, the clock generator is active from time 0 to as long as the circuit is powered on. Example: module clock_gen (output reg clock); //Initialize clock at time zero initial clock = 1'b0; //Toggle clock every half-cycle (time period = 20) always #10 clock = ~clock; initial #1000 $finish; endmodule In the given example, the always statement starts at time 0 and executes the statement clock = ~clock every 10 time units. Notice that the initialization of clock has to be done inside a separate initial statement. If we put the initialization of cl...

Structured Procedures: used in behavioral modelling There are two structured procedure statements in Verilog: always and initial. These statements are the two most basic statements in behavioral modeling. All other behavioral statements can appear only inside these structured procedure statements. Verilog is a concurrent programming language unlike the C programming language, which is sequential in nature. Activity flows in Verilog run in parallel rather than in sequence. Each always and initial statement represents a separate activity flow in Verilog. Each activity flow starts at simulation time 0. The statements always and initial cannot be nested. 1. Initial Statement All statements inside an initial statement constitute an initial block. An initial block starts at time 0, executes exactly once during a simulation, and then does not execute again. If there are multiple initial blocks, each block starts to execute concurrently at time 0. Each block finishes execution in...

Getting start with MATLAB Launch MATLAB Software and type the following code on command prompt and check the output.  To initialize a scalar a: >>a=[2] To initialize a row vector b: >>b=[1 2 3 4 5] Note that spaces between numbers signify a new column. To initialize a column vector c: >>c=[6; 7; 8; 9] Note that semicolons between numbers signify a new row. To initialize a 3 by 3 matrix M: >>M=[1 2 3; 4 5 6; 7 8 9] Again, spaces between numbers signify a new column, whereas semicolons signify a new row.